1. Field of the Invention
The present invention relates generally to a method of testing semiconductor integrated circuits and more particularly to a method of characterizing A.C. performance of an integrated circuit during D.C. parametric testing.
2. Description of Related Art
FIG. 1 is a simplified block diagram representing typical conventional methods of manufacturing complex integrated circuits. As indicated by element 10, the integrated circuits are first fabricated. At this stage of the process, the circuits are in wafer form, with a single wafer containing hundreds or even thousands of individual integrated circuits.
Since processes for fabricating integrated circuits are complex and since such processes may vary over time, it is preferable to provide some means for monitoring the fabrication process at an early stage of the manufacture. Typically, each wafer includes one or more process monitor die, each of which contains one or more test patterns. These test patterns are designed to detect changes in the fabrication process.
As represented by block 12, electrical tests are carried out utilizing the process monitor die. These tests are typically carried out using a wafer prober in conjunction with a parametric tester. The wafer prober, which is automated, steps from one process monitor die to another and provides electrical connections to the test pattern circuits. In addition, the prober provides connections for powering the circuits, for supplying input test signals to the circuits and connections for the output signals to be measured. The parametric tester provides the power and input signals and measures the output signals.
At this stage of the manufacturing process, it is practical only to measure the D.C. characteristics of the integrated circuits. These characteristics include threshold voltages, saturation voltages and the like. One reason for this limitation is because a wafer prober typically has poor frequency performance (narrow bandwidth) and is not capable of efficiently coupling higher frequency A.C. signals to the circuits. It is generally not practical to screen for A.C. characteristics until the wafer has been broken into individual die and the die have been mounted in packages.
In some instances, limited functional testing is carried out on the integrated products. The purpose of such functional testing, which may require the use of relatively low frequency input signals, is to determine whether the circuit will function even at low speed. Although such functional testing may provide limited information regarding A.C. performance, the testing cannot usually be carried out using a D.C. parametric tester exclusively. In addition, the A.C. performance which is measured in this manner is dependent upon the type and nature of the integrated circuit product.
Once the D.C. characteristics of the process monitor die have been measured, the wafer is scribed and broken. The die are sorted, as shown by block 14, in accordance with the results of the D.C. and functionality testing. At this stage, many of the die are discarded. The die that pass the D.C. and functionality screening are then assembled as indicated by element 16. This involves mounting the die in packages and connecting the die to the package leads using bonding wire or the like.
Once the circuits are assembled, the final tests are carried out as shown by block 18. The final tests include A.C. testing of the packaged parts. This A.C. testing typically includes functional tests of the integrated circuit devices and therefore measures both A.C. and D.C. performance. Those integrated circuit devices which pass the final tests are then placed in inventory or stock for sale, as indicated by block 20.
The previously described prior art manufacturing process, where A.C. testing occurs only after assembly, possesses several serious shortcomings. By way of example, it is very costly to sort parts (block 14) and to assemble parts (block 16) which have passed D.C. screening (block 12), but which will eventually fail functional A.C. testing (block 18).
A further shortcoming arises when circuits are fabricated in one location and are transported to another location for assembly. Typically, the assembled parts are returned to the fabrication facility for final testing. In the event there are problems with the fabrication process which affect only A.C. performance and not D.C. performance, the process problems will not be discovered for quite some time, commonly on the order of several weeks. Meanwhile, large numbers of defective parts will have been fabricated, sorted and assembled.
A still further shortcoming of the above-described manufacturing process arises when the process is transferred from one location to another. For example, it is common for a company to design a new integrated circuit device and to develop a process for manufacturing the circuit. Once the circuit is designed and the process optimized, another facility, such as a foundry, is utilized to perform the initial manufacturing steps. These steps include fabrication (block 10) and D.C. screening (block 12). The devices are then typically shipped to the main plant for sorting (block 14) and for assembly (block 16) and final test (block 18).
The process at the main plant must be successfully transferred to the foundry. A process that is developed on a prototype line for transfer to a foundry is typically specified by a set of measurable electrical parameters, such as threshold voltage and the like. The purpose of such specifications is to guarantee a known range of circuit characteristics, including both D.C. and A.C. performance.
When a process is transferred to a foundry, it is possible that parameters which cannot be measured electrically will vary in a direction which degrades A.C. performance. Further, parameters which can be measured electrically are located within the associated specification range differently than in the original process, frequently in a direction which degrades performance. The result is a transferred process which meets the original specification, but the A.C. performance does not meet the expectations established by samples from the prototype lines.
The present invention overcomes the above-noted shortcomings of prior art integrated circuit manufacturing processes. In accordance with the present invention, parameters relating to A.C. performance characteristics can be readily measured at the first electrical test stage (block 12) while the devices are still in wafer form utilizing a unique process monitor circuit. Since the process monitor circuit is separate from the principal integrated circuit devices on the wafer and since the process monitor can be standardized, A.C. performance characteristics can be reliably measured, independent of the type of principal integrated circuit device. Furthermore, the measurements made utilizing the process monitor circuit can be carried out utilizing conventional parametric testing equipment capable of making D.C. measurements only. In addition, the parameters relating to A.C. performance can be made with a wafer prober despite the bandwidth limitations of the wafer probe head.
The present invention permits devices which would not meet A.C. performance specifications normally measured at final test (block 18) to be eliminated prior to the sorting and assembly thereby resulting in substantial savings. Further, the time required to uncover problems in the fabrication process which adversely affect A.C. performance is greatly reduced. In addition, a process can be readily transferred to a foundry with a set of specifications which can be measured at the foundry using conventional D.C. parametric testing equipment and which can predict both A.C. and D.C. performance. These and other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Preferred Embodiment together with the drawings.